This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-195173, filed Jun. 28, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly, a synchronous DRAM that executes an auto precharge operation.
2. Description of the Related Art
A synchronous DRAM (hereinafter referred to as an xe2x80x9cSDRAMxe2x80x9d) that operates in synchronism with an external clock has an operation mode called xe2x80x9cauto precharge (bank precharge)xe2x80x9d.
In the auto precharge mode, in the memory chip of the DRAM, the potential of a presently-selected word line in a bank automatically shifts to a non-selection potential (e.g. the ground potential), and preparation processing for the next processing (for example, shifting the potential of a word line in the same bank to be selected next to a selection potential), i.e. bank precharge, is executed.
FIG. 1 shows an essential part of a conventional SDRAM having the auto precharge mode.
In the structure shown in FIG. 1, in the write mode, a burst length counter 12 is activated to thereby latch a burst signal and set a column select line enable signal CPSRX at xe2x80x9cHxe2x80x9d. When the level of the column select line enable signal CPSRX rises to xe2x80x9cHxe2x80x9d, a column clock generator 13 is activated. The column clock generator 13 outputs a control signal CSLCK for controlling the potential of a column select line CSL.
A clock CLKIN (=VCLK) is input to the column clock generator 13 and an auto precharge shift register 15. After finishing the column burst operation, the column select line enable signal CPSRX lowers to xe2x80x9cLxe2x80x9d.
When a write and auto precharge command is input to an input receiver/command decoder 11, an auto precharge signal AUTPL is input to an auto precharge decoder 14. The auto precharge decoder 14, in turn, generates an auto precharge enable signal AUTPE based on the column select line enable signal CPSRX and the auto precharge signal AUTPL.
The auto precharge enable signal AUTPE is input to the auto precharge shift register 15, where it is shifted by tWR in synchronism with the clock CLKIN and output as a signal AUTPG. A bank controller 16 outputs a bank precharge signal BNK based on the signal AUTPG. As a result, bank precharge is executed, and the potential WL of a presently-selected word line is shifted from the selection potential to a non-selection potential.
FIG. 2 illustrates a concrete example of the auto precharge decoder 14 appearing in FIG. 1. The auto precharge decoder 14 comprises inverters 11 and 12 and a NAND circuit NA1. Further, FIGS. 3A and 3B illustrate a concrete example of the auto precharge shift register 15 appearing in FIG. 1.
FIG. 4 shows signal waveforms in the write and auto precharge mode.
The auto precharge mode is provided in, for example, a double data rate (DDR) type SDRAM.
In the write operation of the DDR type SDRAM, data VDQ is not input into the chip in synchronism with a command cycle, but a predetermined clock cycle is necessary until the data is started to be input after the command cycle finishes. This is called xe2x80x9cwrite latency (hereinafter referred to as xe2x80x9cWCLxe2x80x9d)xe2x80x9d. In the waveforms of FIG. 4, WCL is set at 1.
Further, in the DDR type SDRAM, when inputting the data VDQ into the chip, a dedicated input trigger, called xe2x80x9cDQS (=VDQS)xe2x80x9d, is used. Specifically, the data VDQ is input into the chip in synchronism with the edges of the trigger DQS. Further, the trigger DQS usually has a phase shift from an external clock VCLK. This phase shift is called a xe2x80x9cDQS skewxe2x80x9d. In the waveforms in FIG. 4, the DQS skew is set at 0.
In the write operation, data is input into the chip, and then the potential of the column select line CSL is raised, thereby writing the data into the memory cells of a selected column. For this reason, when writing a plurality of continuously input data items into memory cells, a predetermined time period is required after all the data items are input to the chip until the last data item is actually written into a memory cell.
To secure the predetermined time period, a write recovery time tWR is prepared. The write recovery time tWR is the period of time that elapses from the time the first external clock pulse signal occurs immediately after the input of the last data item into the chip, to the time the next external clock pulse occurs. In the DDR type SDRAM, the bank precharge command is not allowed to be input into the chip until said next external clock pulse occurs.
This is because if the bank precharge command is input into the chip before the write recovery time tWR elapses, bank precharge is started and the potential of the presently-selected work line WL shifts to the non-selection level, for the next operation, before the last data item is written into a memory cell, resulting in a write error.
The process of setting the write recovery time tWR is, of course, required even in the write and auto precharge mode in which no precharge command is needed.
In the write and auto precharge mode, the auto precharge enable signal AUTPE is shifted by tWR using the external clock VCLK (=CLKIN), thereby executing bank precharge and shifting the potential of the presently-selected work line WL to the non-selection level for the next operation after the last data item is written into the chip.
The above operation will be described in more detail. First, when a bank active command BA is input, the level of a bank active signal BNK rises to xe2x80x9cHxe2x80x9d, thereby raising the potential of a word line WL selected by a row address signal. Subsequently, a write command WT is input, whereby a burst enable signal CPSRX is activated, i.e. rises to xe2x80x9cHxe2x80x9d, after a number of pulses of the external clock corresponding to the write latency WCL are output. As a result, an operation for column selection is started.
More specifically, when the burst enable signal CPSRX is at xe2x80x9cHxe2x80x9d, the external clocks VCLK and DQS are input, whereby the column dedicated clock CSLCK rises to xe2x80x9cHxe2x80x9d to activate the column decoder. Consequently, the potential of the column select line CSL is raised on the basis of a column address signal, thereby writing data into a memory cell selected by the selected column.
After the last one of continuous data items having a predetermined burst length is written into a memory cell, bank precharge is executed and the potential of the presently-selected word line WL is lowered, in preparation for the next processing (for, for example, shifting the potential of a word line in the same bank to be selected next to the selection potential).
In the waveforms of FIG. 4, since tWR=1, the potential of the word line WL is lowered when one pulse of the external clock has risen after the rising of one pulse of the external clock immediately after the last data item is input into the chip.
In order to write all the continuous data items of the predetermined burst length into memory cells, the time xcex94t1 required from the rising of the potential of the column select line CSL to the falling of that of the selected word line WL must be greater than the time xcex94t2 required from the rising of the potential of the column select line CSL to the writing of all the data items into the memory cells, as is shown in FIG. 5.
When xcex94t1 greater than xcex94t2, the difference xcex94t3 therebetween acts as a margin for the time required for writing data into the memory cells.
In general, in the waveforms shown in FIG. 5, the number of clock pulses defines tWR. If the number of clock pulses that define tWR is constant (e.g. 1), the faster the transistors operate or the higher the frequency of the external clock, the shorter xcex94t1 is.
However, xcex94t2 is the time necessary to write all data into the memory cells, and hence significantly depends upon the capacity and resistance, etc. of bit lines BL or the memory cells. Accordingly, even when the transistors operate at high speed or the frequency of the external clock is high, xcex94t2 is not as shortened as xcex94t1.
This being so, the margin xcex94t3 for the time required to write data into memory cells becomes very short. In some cases, xcex94t3 disappears and xcex94t2 is greater than xcex94t1, thereby causing a write error, as is shown in FIG. 6.
Furthermore, in a DDR type SDRAM having the signal DQS, it is possible that a skew of xe2x80x9cxcex94t4xe2x80x9d may occur between the data input signal VDQS (=DQS) and the external clock VCLK (=CLKIN) as shown in FIG. 7. Since the column select line CSL is activated in synchronism with the signal DQS, if the signal DQS delays from the external clock VCLK, the column select line CSL is activated after a period of time corresponding to the delay of the signal DQS elapses. Accordingly, the time required for writing data into memory cells is lengthened.
The point of time at which the potential of the selected word line WL is lowered corresponds to the rising time of the external clock VCLK, and hence is always constant. Accordingly, it is possible that the time required for writing data into memory cells is lengthened, the margin xcex94t3 disappears, and xcex94t2 becomes greater than xcex94t1, thereby causing a write error, as is shown in FIG. 7.
To prevent the write error, a method could be devised where the number of clock pulses for determining tWR is increased, for example, from 1 to 2, as is shown in FIG. 8. In this case, since the point of time at which the level of the signal AUTPG rises to xe2x80x9cHxe2x80x9d delays, the time xcex94t1 is lengthened which is required until the potential of the word lines is lowered after the potential of the column line CSL is raised. Accordingly, the difference xcex94t3 between xcex94t1 and xcex94t2 (required until data is written into memory cells after the potential of the column select line CSL is raised) can be secured, thereby preventing write errors.
In the prior art, however, the above-mentioned measure, i.e. shifting the auto precharge enable signal AUTPE by two clock pulses, using the clock CLKIN, requires a big change in the circuit structure of the auto precharge shift register 15 shown in FIG. 1. In other words, the existing circuit (tWR corresponds to one clock pulse) cannot be used without changes, and a lot of time is required to design and develop a suitable circuit.
It is the object of the present invention to provide a semiconductor memory completely free from a write error without changing the number of clock pulses that defines a write recovery time tWR (i.e. without a big change in circuit structure), even if the transistors incorporated therein are designed to operate at higher speeds and/or the frequency of an external clock is increased.
To attain the object, there is provided a semiconductor memory comprising: a generator for generating a pulse signal, used to operate a column decoder, on the basis of a clock signal and a first control signal; a precharge decoder for outputting a second control signal, used to control an operation of a row decoder, on the basis of the first control signal and the pulse signal; and a delay circuit operable independent of the clock signal for delaying the second control signal by a predetermined time period.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.